Increasing throughput in IEEE 802.11 by optimal selection of backoff parameters

Engineering and Physical Sciences Research Council. Grant Number: EP/G012628/

Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures

Cryogenic CMOS is a crucial subcomponent of quantum-technological applications, particularly as control electronics for quantum computers. Simulation is an important first step in designing any CMOS circuit. However, the standard BSIM4.5 model is only applicable for temperatures between 230 K and 420 K. In this work, N-type MOSFETs with different dimensions in a 65-nm CMOS technology were characterized at room temperature and liquid helium temperature (4.2 K). These measurements were compared with corresponding simulations from the BSIM4.5 model. A model of drain current in the triode region was constructed, where key parameters, such as threshold voltage and effective mobility, were modified. By adjusting these temperature-dependent parameters, the modified model predicted the triode region currents with an error reduced to 7.6%. Thus, the modified model can be utilized to simulate transistor behavior in the triode region at cryogenic temperatures

1.2V Energy-Efficient Wireless CMOS Potentiostat for Amperometric Measurements

Wireless biosensors are playing a pivotal role in health monitoring, disease detection and management. The development of wireless biosensor nodes and networks strongly relies on the design of novel low-power, low-cost and flexible CMOS sensor readouts. This paper presents a CMOS potentiostat that integrates a control amplifier, a dual-slope ADC and a wireless unit on the same chip. It implements a novel time-based readout scheme, whereby the counter of the dual-slope ADC is moved to the receiver and the sensor current is encoded in the timing between two wireless pulses transmitted via pulse-harmonic modulation across an inductive link. Measured results show that the potentiostat chip can resolve a minimum input current of 10pA at a sampling frequency of 125 Hz and a power consumption of 12 μW

A utility based framework for optimal network measurement

Packet level measurement is now routinely used to evaluate the loss and delay performance of broadband networks. In active measurement, probe packets provide samples of the loss and delay and from these samples the performance of the traffic as a whole can be deduced. However this is prone to errors: inaccuracy due to taking insufficient samples, self-interference due to injecting too many probe packets, and possible sample-correlation induced bias. In this paper we consider the optimisation of probing rate by treating all measurements as numerical experiments which can be optimally designed by using the statistical principles of design of experiments. We develop an analytical technique that quantifies an overall utility function associated with: (i) the disruption caused per probe packet, (ii) the bias and (iii) the variance as a function of the probing (sampling) rate. Our numerical results show that the optimal probing rate depends strongly on what parameter the network engineer seeks to measure.</p

An Integrated Passive Phase-Shift Keying Modulator for Biomedical Implants With Power Telemetry Over a Single Inductive Link

This paper presents a passive phase-shift keying (PPSK) modulator for uplink data transmission for biomedical implants with simultaneous power and data transmission over a single 13.56 MHz inductive link. The PPSK modulator provides a data rate up to 1.35 Mbps with a modulation index between 3% and 38% for a variation of the coupling coefficient between 0.05 and 0.26. This modulation scheme is particularly suited for biomedical implants that have high power demand and low coupling coefficients. The PPSK modulator operates in conjunction with on-off-keying downlink communication. The same inductive link is used to provide up to 100 mW of power to a multi-channel stimulator. The majority of the system on the implant side was implemented as an application specific integrated circuit (ASIC), fabricated in 0.6-[Formula: see text] high voltage CMOS technology. The theory of PPSK modulation, simulated and measured performance evaluation, and comparison with other state-of-the-art impedance modulation techniques is presented. The measured bit error rate around critical coupling at 1.35 Mbps is below 6 ×10(-8)

Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

There is growing demand for circuits that can provide ever greater performance from a minimal power budget. Example applications include wireless sensor nodes, mobile devices, and biomedical implants. High speed clock circuits are an integral part of such systems, playing roles such as providing digital processor clocks, or generating wireless carrier signals; this clock generation can often take a large part of a system’s power budget. Common techniques to reduce power consumption generally involve reducing the clock speed, and/or complex designs using a large circuit area. This paper proposes an alternative method of clock generation based on driving a high-Q resonator with a periodic chain of impulses. In this way, power consumption is reduced when compared to traditional resonator based designs; this power reduction comes at the cost of increased period jitter. A circuit was designed and laid out in 0.18µm CMOS, and was simulated in order to test the technique. Simulation results suggest that the circuit can achieve a FoM of 4.89GHz/mW, with a peak period jitter of 10.2ps at 2.015GHz, using a model resonator with a Q-factor of 126

An Energy-Efficient 1.2V 4-Channel Wireless CMOS Potentiostat for Amperometric Biosensors

Point-of-care (PoC) diagnostics rely on the design of low-power and miniaturized readout units that can offer rapid and accurate test results, replacing the need for specialized equipment. CMOS technology can be exploited in order to design complex systems while achieving high energy efficiency for suitable operation in a mobile settings. This paper presents the design of a novel energy-efficient 4-channel wireless potentiostat chip, based on a dual-slope ADC architecture, that features a low-complexity wireless unit and a calibration approach that does not require additional circuitry. The chip was designed in a 0.35μm CMOS process. The simulated results suggest that each potentiostat channel can achieve an estimated energy efficiency of 2.5 pJ/bit from a 1.2 V supply

Single-pulse harmonic modulation for short range biomedical inductive data transfer

Short-range, low-power, high data-rate telemetry is an increasingly desirable feature for implantable medical devices (IMDs), and is commonly implemented using an inductive link. Pulse Harmonic Modulation (PHM) provides the desired high data rates and low power consumption, but requires precise pulse timing. This paper presents a modification of PHM, Single-Pulse Harmonic Modulation (SPHM), which offers reduced power consumption and lower implementation complexity. In order to test the SPHM concept, transmitter and receiver circuits were designed in 0.35μm CMOS and simulated. The simulated results suggest that the circuits can transceive data at 50Mb/s, consuming 1.49pJ/b and 2.59pJ/b at the transmitter and receiver respectively, from a 1.2V supply

Short-Range Quality-Factor Modulation (SQuirM) for Low Power High Speed Inductive Data Transfer

Wireless data telemetry for implantable medical devices (IMDs) has, in general, been limited to a few Mbps, and used for applications such as transmitting recordings from an implanted monitoring device, or uploading commands to an implanted stimulator. However, modern neural interfaces need to record high resolution potentials from hundreds of neurons; this requires much higher data rates. While fast wireless communication is possible using existing standards such as WiFi, power consumption demands are far too high for IMDs. Short range inductive link based telemetry, in particular impulse-based systems such as pulse-harmonic modulation (PHM), have demonstrated transfer speeds of up to 20, Mbps with a small power budget. However, these systems require complex and precise circuits, making them potentially susceptible to inter-symbol-interference. This work presents a new method named Short-range Quality-factor Modulation (SQuirM), which retains the low power consumption and high data rate of PHM, while improving the resilience of the system and simplifying the circuit design. Transmitter and receiver circuits were fabricated using 0.35, μm CMOS. The circuits were capable of reliably transceiving data at speeds of up to 50.4, Mbps, with a BER of <4.5 x 10^{-10}, and a transmitter energy consumption of 8.11 pJ/b